- List
- EU dual-use list – Annex I to Regulation (EU) 2021/821, updated annually
- Originating regime
- Thỏa ước Wassenaar
a. "Technology" according to the General Technology Note, for the "development", "production" or "use" of equipment or "software" specified in 4A or 4D;
b. "Technology", according to the General Technology Note, other than that specified in 4E001.a., for the "development" or "production" of equipment as follows:
1. "Digital computers" having an "Adjusted Peak Performance" ("APP") exceeding 24 Weighted TeraFLOPS (WT);
2. "Electronic assemblies" specially designed or modified for enhancing performance by aggregation of processors so that the "APP" of the aggregation exceeds the limit in 4E001.b.1.;
3. Items specified by 4A506.b. or 4A506.c.
c. "Technology" for the "development" of "intrusion software".
Note 1:
4E001.a. and 4E001.c. do not control "vulnerability disclosure" or "cyber incident response".
Note 2:
Note 1 does not diminish the rights of the competent authority of the EU Member State in which the exporter is established to ascertain compliance with 4E001.a. and 4E001.c.
TECHNICAL NOTE ON "ADJUSTED PEAK PERFORMANCE" ("APP")
"APP" is an adjusted peak rate at which "digital computers" perform 64-bit or larger floating point additions and multiplications.
"APP" is expressed in Weighted TeraFLOPS (WT), in units of 1012 adjusted floating point operations per second.
Abbreviations used in this Technical Note
n
number of processors in the "digital computer"
i
processor number (i,...n)
ti
processor cycle time (ti = 1/Fi)
Fi
processor frequency
Ri
peak floating point calculating rate
Wi
architecture adjustment factor
Outline of "APP" calculation method
1. For each processor i, determine the peak number of 64-bit or larger floating point operations, FPOi, performed per cycle for each processor in the "digital computer".
Note:
In determining FPO, include only 64-bit or larger floating point additions or multiplications. All floating point operations must be expressed in operations per processor cycle; operations requiring multiple cycles may be expressed in fractional results per cycle. For processors not capable of performing calculations on floating point operands of 64-bit or more, the effective calculating rate R is zero.
2. Calculate the floating point rate R for each processor Ri = FPOi/ti.
3. Calculate "APP" as "APP" = W1 × R1 + W2 × R2 + … + Wn × Rn.
4. For 'vector processors', Wi = 0,9. For non-'vector processors', Wi = 0,3.
Note 1:
For processors that perform compound operations in a cycle, such as addition and multiplication, each operation is counted.
Note 2:
For a pipelined processor the effective calculating rate R is the faster of the pipelined rate, once the pipeline is full, or the non-pipelined rate.
Note 3:
The calculating rate R of each contributing processor is to be calculated at its maximum value theoretically possible before the "APP" of the combination is derived. Simultaneous operations are assumed to exist when the computer manufacturer claims concurrent, parallel, or simultaneous operation or execution in a manual or brochure for the computer.
Note 4:
Do not include processors that are limited to input/output and peripheral functions (e.g., disk drive, communication and video display) when calculating "APP".
Note 5:
"APP" values are not to be calculated for processor combinations (inter)connected by "Local Area Networks", Wide Area Networks, I/O shared connections/devices, I/O controllers and any communication interconnection implemented by "software".
Note 6:
"APP" values must be calculated for processor combinations containing processors specially designed to enhance performance by aggregation, operating simultaneously and sharing memory.
Technical Notes:
1. Aggregate all processors and accelerators operating simultaneously and located on the same die.
2. Processor combinations share memory when any processor is capable of accessing any memory location in the system through the hardware transmission of cache lines or memory words, without the involvement of any software mechanism, which may be achieved using "electronic assemblies" specified in 4A003.c.
Note 7:
A 'vector processor' is defined as a processor with built-in instructions that perform multiple calculations on floating-point vectors (one-dimensional arrays of 64-bit or larger numbers) simultaneously, having at least 2 vector functional units and at least 8 vector registers of at least 64 elements each.
b. "Technology", according to the General Technology Note, other than that specified in 4E001.a., for the "development" or "production" of equipment as follows:
1. "Digital computers" having an "Adjusted Peak Performance" ("APP") exceeding 24 Weighted TeraFLOPS (WT);
2. "Electronic assemblies" specially designed or modified for enhancing performance by aggregation of processors so that the "APP" of the aggregation exceeds the limit in 4E001.b.1.;
3. Items specified by 4A506.b. or 4A506.c.
c. "Technology" for the "development" of "intrusion software".
Note 1:
4E001.a. and 4E001.c. do not control "vulnerability disclosure" or "cyber incident response".
Note 2:
Note 1 does not diminish the rights of the competent authority of the EU Member State in which the exporter is established to ascertain compliance with 4E001.a. and 4E001.c.
TECHNICAL NOTE ON "ADJUSTED PEAK PERFORMANCE" ("APP")
"APP" is an adjusted peak rate at which "digital computers" perform 64-bit or larger floating point additions and multiplications.
"APP" is expressed in Weighted TeraFLOPS (WT), in units of 1012 adjusted floating point operations per second.
Abbreviations used in this Technical Note
n
number of processors in the "digital computer"
i
processor number (i,...n)
ti
processor cycle time (ti = 1/Fi)
Fi
processor frequency
Ri
peak floating point calculating rate
Wi
architecture adjustment factor
Outline of "APP" calculation method
1. For each processor i, determine the peak number of 64-bit or larger floating point operations, FPOi, performed per cycle for each processor in the "digital computer".
Note:
In determining FPO, include only 64-bit or larger floating point additions or multiplications. All floating point operations must be expressed in operations per processor cycle; operations requiring multiple cycles may be expressed in fractional results per cycle. For processors not capable of performing calculations on floating point operands of 64-bit or more, the effective calculating rate R is zero.
2. Calculate the floating point rate R for each processor Ri = FPOi/ti.
3. Calculate "APP" as "APP" = W1 × R1 + W2 × R2 + … + Wn × Rn.
4. For 'vector processors', Wi = 0,9. For non-'vector processors', Wi = 0,3.
Note 1:
For processors that perform compound operations in a cycle, such as addition and multiplication, each operation is counted.
Note 2:
For a pipelined processor the effective calculating rate R is the faster of the pipelined rate, once the pipeline is full, or the non-pipelined rate.
Note 3:
The calculating rate R of each contributing processor is to be calculated at its maximum value theoretically possible before the "APP" of the combination is derived. Simultaneous operations are assumed to exist when the computer manufacturer claims concurrent, parallel, or simultaneous operation or execution in a manual or brochure for the computer.
Note 4:
Do not include processors that are limited to input/output and peripheral functions (e.g., disk drive, communication and video display) when calculating "APP".
Note 5:
"APP" values are not to be calculated for processor combinations (inter)connected by "Local Area Networks", Wide Area Networks, I/O shared connections/devices, I/O controllers and any communication interconnection implemented by "software".
Note 6:
"APP" values must be calculated for processor combinations containing processors specially designed to enhance performance by aggregation, operating simultaneously and sharing memory.
Technical Notes:
1. Aggregate all processors and accelerators operating simultaneously and located on the same die.
2. Processor combinations share memory when any processor is capable of accessing any memory location in the system through the hardware transmission of cache lines or memory words, without the involvement of any software mechanism, which may be achieved using "electronic assemblies" specified in 4A003.c.
Note 7:
A 'vector processor' is defined as a processor with built-in instructions that perform multiple calculations on floating-point vectors (one-dimensional arrays of 64-bit or larger numbers) simultaneously, having at least 2 vector functional units and at least 8 vector registers of at least 64 elements each.