- List
- EU dual-use list – Annex I to Regulation (EU) 2021/821, updated annually
- Originating regime
- Thỏa ước Wassenaar
a. A 'vector processor unit' designed to perform more than two calculations on 'floating-point' vectors (one-dimensional arrays of 32-bit or larger numbers) simultaneously;
Technical Note:
For the purposes of 3E002.a., a 'vector processor unit' is a processor element with built-in instructions that perform multiple calculations on 'floating-point' vectors (one-dimensional arrays of 32-bit or larger numbers) simultaneously, having at least one vector arithmetic logic unit and vector registers of at least 32 elements each.
b. Designed to perform more than four 64-bit or larger 'floating-point' operation results per cycle; or
c. Designed to perform more than eight 16-bit 'fixed-point' multiply-accumulate results per cycle (e.g., digital manipulation of analogue information that has been previously converted into digital form, also known as digital "signal processing").
Technical Notes:
1. For the purposes of 3E002.a. and 3E002.b., 'floating-point' is defined by IEEE-754.
2. For the purposes of 3E002.c., 'fixed-point' refers to a fixed-width real number with both an integer component and a fractional component, and which does not include integer-only formats.
Note 1:
3E002 does not control "technology" for multimedia extensions.
Note 2:
3E002 does not control "technology" for micro-processor cores, having all of the following:
a. Using "technology" at or above 0,130 μm;
and
b. Incorporating multi-layer structures with five or fewer metal layers.
Note 3:
3E002 includes "technology" for the "development" or "production" of digital signal processors and digital array processors.
Technical Note:
For the purposes of 3E002.a., a 'vector processor unit' is a processor element with built-in instructions that perform multiple calculations on 'floating-point' vectors (one-dimensional arrays of 32-bit or larger numbers) simultaneously, having at least one vector arithmetic logic unit and vector registers of at least 32 elements each.
b. Designed to perform more than four 64-bit or larger 'floating-point' operation results per cycle; or
c. Designed to perform more than eight 16-bit 'fixed-point' multiply-accumulate results per cycle (e.g., digital manipulation of analogue information that has been previously converted into digital form, also known as digital "signal processing").
Technical Notes:
1. For the purposes of 3E002.a. and 3E002.b., 'floating-point' is defined by IEEE-754.
2. For the purposes of 3E002.c., 'fixed-point' refers to a fixed-width real number with both an integer component and a fractional component, and which does not include integer-only formats.
Note 1:
3E002 does not control "technology" for multimedia extensions.
Note 2:
3E002 does not control "technology" for micro-processor cores, having all of the following:
a. Using "technology" at or above 0,130 μm;
and
b. Incorporating multi-layer structures with five or fewer metal layers.
Note 3:
3E002 includes "technology" for the "development" or "production" of digital signal processors and digital array processors.